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Tutorials
1. Injection locked oscillators: applications, modeling, and design Sunday 7 June 2015, morning Speaker: Tony Chan Carusone (Integrated Systems Laboratory, University of Toronto, Canada) Abstract Injection-locked oscillators (ILOs) have experienced increasing use for wireless RF communication and in clocking circuitry for wireline links. This presentation begins with some background on ILOs, highlighting their benefits compared with DLLs, PLLs and other circuitry capable of clock amplification, multiplication, phase generation, interpolation, and phase noise filtering. A challenge limiting the practical use of ILOs in these applications is that their modeling is less well understood. This tutorial will therefore summarize the analysis and practical modeling methods for ILOs. First, the classical linearized model is presented. The intuitive understanding afforded by the linearized model will be highlighted and it will be used to inform high-level design choices. Second, the impulse sensitivity function, a cyclo-stationary approach popularized for modeling phase noise in oscillators, is applied to the modeling of ILOs. Finally, a more accurate model, called the phase transfer characteristic, is described, including methods for model extraction. A live demo of ILO modeling for practical applications will be incorporated into the tutorial using Matlab/Simulink. The tutorial will then overview the design of ILOs for several practical applications. First, multi-phase clock generation is covered and techniques to ensure uniform spacing of the generated phases are described. Second, the use of ILOs for phase interpolation is discussed. A key challenge here is the ability to provide a clock phase programmable over the entire range ±π radians. For example, some past work in this area has observed that an ILO's performance suffers when used for phase shifts exceeding ±π/2 radians. This problem may be addressed by selectively injecting either the in-phase or quadrature stage of a quadrature ILO, thereby providing an additional 90-degree phase shift. Implementations of this approach are described including both ring and LC oscillators operating at frequencies from 2 - 20 GHz in CMOS technologies from 65nm - 130nm. Finally, approaches towards the design of an ILO for clock multiplication are reviewed. Particular attention is paid to the need to ensure adequate lock range for frequency-agile applications. A useful approach in this regard is to ensure strong injection via multiple sites in the oscillator, demonstrated in a 4x multiplying ILO implemented in 40nm CMOS. The tutorial will culminate in two detailed design case studies from the presenter’s past work that combine multiple ILOs into highly-functional clocking subsystems. First, a high-frequency jitter-tolerant receiver in 65 nm CMOS is presented. The clock receiver comprises two ILOs to frequency-multiply, deskew, and adjust jitter tracking bandwidth. Jitter tolerance is improved by tracking correlated jitter through the ILOs. Different data rates and latency mismatch between the clock and data paths are accommodated by controlling the ILOs’ jitter tracking bandwidth up to 300 MHz. A receiver using this architecture in 65nm CMOS consumes 0.92 pJ/bit operating at 7.4 Gb/s and has a jitter tolerance of 1.5 UI at 200 MHz. Second, a frequency agile multiplying injection-locked oscillator (MILO) suitable for fast power cycling is presented. Edge detectors and multiple injection sites extend the aggregate lock range of two MILOs to 55.7% of the 3.16-GHz center frequency. Monitoring circuits identify the correct MILO and power-off the other within 10 reference clock cycles. Table of Contents
Biography Tony Chan Carusone received his Ph.D. at the University of Toronto in 2002. Since then, he has been with the Department of Electrical and Computer Engineering at the University of Toronto where he is currently a Professor and the department’s Associate Chair, Research. He is a Senior Member of the IEEE, has co-authored the best paper at the 2005 Compound Semiconductor Integrated Circuits Symposium, the best student papers at the 2007, 2008, and 2011 Custom Integrated Circuits Conferences, and the best invited paper at the 2010 Custom Integrated Circuits Conference. He was the Editor-in-Chief of the IEEE Transactions on Circuits and Systems II: Express Briefs and a member of the Technical Program Committee for the International Solid-State Circuits Conference. He currently serves on the editorial board of the IEEE Journal of Solid-State Circuits and on the Technical Program Committee for the VLSI Circuits Symposium. He is a regular consultant to industry in the areas of analog, mixed-signal, and communication integrated circuit design, and is an author, along with David Johns and Ken Martin, of the 2nd edition of the classic textbook "Analog Integrated Circuit Design". Relevant Recent Published Work [1] D. Dunwell, A. Chan Carusone, “Modeling Oscillator Injection Locking Using the Phase Domain Response,” IEEE Transactions on Circuits and Systems I, pp. 2823-283, November 2013. [2] M. Hossain, A. Chan Carusone, "7.4 Gb/s 6.8 mW Source Synchronous Receiver in 65 nm CMOS," IEEE Journal of Solid-State Circuits, vol.46, no.6, pp.1337-1348, June 2011. (Journal of Solid-State Circuits Top 25 Most Downloaded, June 2011) [3] M. Hossain and A. Chan Carusone, “5-10 Gb/s 70mW Burst Mode AC Coupled Receiver in 90nm CMOS,” IEEE Journal of Solid-State Circuits, pp. 524-537, March 2010. [4] M. Hossain and A. Chan Carusone, “CMOS Oscillators for Clock Distribution and Injection-Locked Deskew,” IEEE Journal of Solid-State Circuits, pp. 2138 – 2153, August 2009. (Journal of Solid-State Circuits Top 10 Most Downloaded, August 2009) (IEEExplore Top 100 Most Downloaded, August 2009) [5] D. Dunwell, A. Chan Carusone, J. Zerbe, B. Leibowitz, B. Daly, J. Eble, “A 2.3-4 GHz Injection-Locked Clock Multiplier with 55.7% Lock Range and 10-ns Power-On,” Custom Integrated Circuits Conference, San Jose, California, September 2012. [6] J. Zerbe, B. Daly, W. Dettloff, T. Stone, W. Stonecypher, P. Venkatesan, K. Prabhu, B. Su, J. Ren, B. Tsang, B. Leibowitz, D. Dunwell, A. Chan Carusone, J. Eble, “A 5.6Gb/s 2.4mW/Gb/s Bidirectional Link With 8ns Power-On,” VLSI Circuits Symposium, Kyoto, Japan, June 2011. [7] J. L. Zerbe, B. W. Daly, D. T. Dunwell, A. Chan Carusone, J. C. Eble, “Integrated circuit having multiplying injection-locked oscillator,” US patent appl. no. 14/000,710, filed April 18, 2012. [8] A. Chan Carusone, D. Johns, and K. Martin, Analog Integrated Circuit Design,2nd ed., J. Wiley & Sons, Nov. 2011.
2. FDSOI technology Sunday 7 June 2015, morning Speakers: Philippe Flatresse (STMicroelectronics, Crolles, France); Eric Kerhervé, Aurélien Larie, Baudouin Martineau (IMS Laboratory, Bordeaux, France). Abstract - Part I : Body Biasing techniques in UTBB FDSOI technology (by Philippe Flatresse) With the increasing demand of processing power to be delivered by the System On Chips, it is now key to improve their energy efficiency, not only for thermal or battery life duration purpose but also for environmental considerations such as green supercomputers, wireless base stations and micro servers. Using FD-SOI technology enables designing energy efficient SOCs running at very high frequency over an ultra-wide voltage range while minimizing power dissipation. In this context, STMicroelectronics has developed a full design platform leveraging on body biasing considered as the key design solution to provide best-in class SOCs to the market. The talk will describe the capability of body biasing, showing it is not only well suited for performance boosting but also for power optimization and compensation. Body biasing implementation details will be also shared thru the presentation of several silicon demonstrations. - Part II : Millimeter Wave 28nm-CMOS FD SOI Power Amplifier Design (by Eric Kerhervé, Aurélien Larie & Baudouin Martineau) Traditionally, millimeter-wave (mmW) circuits using only III-V technologies have been used in low-volume, high-performance products. With the recent progress of highly scaled Si-based technologies such as 28nm-CMOS FD SOI achieving fT and fmax beyond 300 GHz, the application area of Si-based technologies has broadened from digital, analog, RF, and microwave domains to include mmW applications. The aim of this tutorial is to give the audience the design flow to successful the mmw power amplifier design in 28nm-CMOS FD SOI technology from STMicroelectronics. Recent developments at 60GHz perform by IMS Bordeaux will illustrate this tutorial from a research activity point of view. Summary of the 60 GHz 28nm-CMOS FD SOI Power Amplifier design flow - Why CMOS FD SOI? - PA structure - Challenge (active device) - PA operating classes - Linearity issues in WPAN applications - Choice of structures and transistor topologies - 28nm CMOS FD SOI transistor performances - Optimal transistor finger width for fmax - Optimal biasing for fT and fmax - Output power and number of transistor fingers - 28nm CMOS FD SOI transistor design - Optimum output impedance determination - Impact of the parasitic interconnections - Extraction of parasitic elements - Stability issues - Impedance matching network design - Simulation and measurement results of the PA Biography Philippe Flatresse received M.S. degree in Electrical Engineering in 1995 and PhD degree in Microelectronics in 1999 from Grenoble institute of technology. During his thesis, he has developed the LETISOI spice model dedicated to SOI technologies at CEA LETI, the R&D laboratory from French Atomic Energy Commission. In year 2000, he joined STMicroelectronics Central R&D to deploy the SOI digital design within the company. He has developed the first SOI standard cells and SRAM libraries as well as IOs including innovative ESD solutions. He has also invented several dedicated CAD tools and low power digital design techniques such as power switches. Thanks to this work, he has pioneered the SOI technology and demonstrated its key advantages for low power high performance digital applications As a design architect, his current research activities are the exploration, development and implementation of ultra-low power platforms able to work in an energy-efficient way on an ultra-wide range of operating points targeting high-growth application areas. His main objective is to explore the energy efficiency limits of parallel computing on multi-cores systems for ultra-low power processing by combining UTBB FD-SOI technology, advanced power management techniques, hardware accelerators and software infrastructure. His current role in ST is in the specification of the appropriate design solutions and technology variants for CMOS products in the following applications area: multimedia processors, consumer products, servers & routers, gaming, low power microcontrollers. His expertise covers bulk and SOI technologies, high performance energy efficient designs, design of libraries and IPs and silicon qualification. He has authored or co-authored more than 50 technical papers, and has filed more than 10 patents in advanced CMOS technologies. Eric Kerhervé received the Ph.D. degree in Electrical Engineering from University of Bordeaux, France in 1994. He joined ENSEIRB-MATMECA and the IMS Laboratory in 1996, where he is currently Professor in Microelectronics and Microwave applications. His main areas of research are the design of RF, microwave and millimeter-wave circuits (power amplifiers and filters) in silicon GaAs and GaN technologies. He is or was involved in several European projects (Medea+ UPPERMOST, Medea+ QSTREAM, Catrene PANAMA, FP6 MOBILIS, ENIAC MIRANDELA), to develop silicon RF/mmW power amplifiers. He has authored or co-authored more than 190 technical papers in this field, and was awarded 23 patents. He has organized 8 RFIC and EuMC workshops on advanced silicon technologies for radiofrequency and millimeter-wave applications. He is involved in the technical program committees of various international conferences (ICECS, IMOC, NEWCAS, EuMIC, SBCCI, LASCAS) and he was the general co-chair of the international IEEE ICECS’2006 and IEEE NEWCAS’2011 conferences. He is co-editor of Special Issues for IEEE-ICECS’2006, IEEE-ICECS’2007, IEEE-LASCAS 2010. He was 2-years associate editor of IEEE Transactions on Circuits and Systems II (TCAS II). He is IEEE senior member and member of the IEEE-CAS, IEEE-MTT and IEEE SSCS societies.
3. Full software radio circuits and systems: design by mathematics in 28nm FDSOI technology and application to 5G standard Sunday 7 June 2015, afternoon Speakers: Yann Deval, François Rivet, Yoan Veyrac, Nassim Bouassida (IMS Laboratory, Bordeaux, France). Abstract The diversity of communication standard simplies the use of multi-band and multi-mode radios. Recent years have seen a wide Investigation on Software Defined Radio for Cognitive Radio application. But, this is always constrained to multi-‐standards prospectives while a complete agility of RF transceivers is required. That is why Full Software Radio proposes to challenge a new way of integrating RF circuits and systems by tackling the main issue: transceiving concurrently any RF signal within a very wide band of interest for telecommunication industry, from 0 to 5GHz for instance. It is clearlyobserved that disruptive solutions are required. The focus of this tutorial will be on the design by mathematics of such RF transceiver design, exploring novel approaches along with a thorough discussion of advanced techniques for these receivers and transmitters towards a revolution in RF integrated circuits and systems. 28nm FDSOI technology from STMicroelectronics will be detailed to demonstrate its strengths in RFIC design. First, a frequency system is presented using a Sampled Analog Signal Processor as a receiver and a Walsh frequency combiner for the transmitter. Then, a temporal system is presented using a wide‐band delta analog to digital converter as a receiver and a RF arbitrary waveform generator, named Riemann Pump for the transmitter. The methodology of every approach will be detailed following the same flow: mathematics, trade‐off with RF electronics integration in 28nm FDSOI, architecture proposal, high level simulation results, circuit design issues, measurement results. Finally, an application to 5G standard will be addressed by demonstrating the feasibility of such systems to carrier aggregation, wide‐band capabilities, low power consumption and high order of modulation schemes. Table of content The goal of this tutorial is to present our original methodology of Full Software Radio system design. The learning objectives address a wide audience:
Wireless system designers have been facing the continuously increasing demand for high data rates and mobility required by new wireless applications and therefore have started research on new generation of wireless systems that are expected to be deployed beyond 2020. For instance, 5G wireless networks will support 1,000‐fold gains in capacity, connections for at least 100 billion devices, and a 10 Gbps individual user experience capable of extremely low latency and response times. Deployment of these networks will emerge between 2020 and 2030. We present 3 main techniques: - SASP Rx is a frequency domain receiver. The principle of the SASP aims at selecting a spectral envelope of a RF signal within a very wide frequency band. To reach this target, the SASP processes analogically the RF input signal spectrum thanks to an analog Discrete Time Fourier Transform (DFT) with discrete time voltage samples. Once the spectrum is processed, voltage samples representing the spectral signal envelope to be treated are converted into digital. The selection of few voltage samples among thousands replaces the classical mixing and filtering operations. It reduces the A/D conversion frequency from GHz frequencies to MHz ones and thus allows a multi band selection at a very low power consumption. Its application for 5G standard is a direct carrier aggregation to achieve a 1Gbps data rate. SASP is a technique developed by IMS in 2010 by Rivet. - Walsh is a frequency domain transmitter. The aim here is to generate any kind of waveform from its spectrum i.e. from its harmonics. For this, and similarly to the Fourier theory, Walsh transform allows decomposing any signal into a series of harmonics. But, instead of building this series on sine waves harmonics, Walsh theorem demonstrates that a family of square waves can generate any kind of signal. Thereby, using a millimeter‐Wave [mmW] Phase‐Locked Loop [PLL], the harmonic generation can be done at low power and area integration cost. It avoids the integration of several voltage controlled oscillators associated to each harmonics of the series. Indeed, square signals can be generated from a high frequency and divide by 2, N times thanks to a mmW PLL. The mathematical theory based on Walsh theorem states that using algebraic operations (phase shifting, sum, delay, ...) on a finite number of square waves allows to implement this signal generator. The originality of this project is that every square signals are directly amplified and then combined by their power to form the transmitted signal with a correct matching. The sum is performed thanks to a current node. Algebraic operations are consequently carried out by biasing differential amplifying square signals. Walsh is a technique developed by IMS in 2013. - Riemann Pump is a time‐domain transmitter. The purpose of the Riemann Pump is to generate arbitrary waveforms up to the gigahertz range with a low cost and low consumption solution, the main target being the generation of modulated signals, especially to address the 5G standard. The wanted signal is to be generated thanks to a pre‐determined set of slopes. At first, the Riemann code is computed from the theoretical desired signal; it corresponds to the slope index sequence giving the better approximation of the signal (within the meaning of the Riemann integral). This code controls switched current sources, in order to produce current steps that are integrated into an output capacitive load, thus generating a piecewise linear approximation of the wanted signal. Riemann is a technique developed by IMS in 2013. Biography Yann DEVAL received his PhD from the University of Bordeaux, France, in 1994. He joined this university in 1993 as an Assistant Professor. In 1999 Pr. Deval became an Associate Professor and created the IC Design Team at IMS. In 2004 he became a Full Professor at ENSEIRB MATMECA. From 2006 to 2010 Pr. Deval was the head of IC Design Group at IMS. Also, from 2010 to 2012 Pr. Deval was the Director of ALBATROS, the advanced research alliance between THALES and the University of Bordeaux for aeronautics and space applications, and since January 2007 he is the Director of ST IMS collaborative joint research laboratory. He was the General Chair of the 2010 RFIC Symposium in Anaheim, CA, and the General Chair of the 2012 ESSCIRC ESSDERC conferences in Bordeaux, France. Pr. Deval published more than 170 papers in international conferences and journals, and holds 46 patents. Francois RIVET received the PhD degree in 2009 from the University of BORDEAUX, France. Since June 2010, he is tenured as Associate Professor at Bordeaux Institute of Technology and IMS Lab, the microelectronics laboratory of the University of BORDEAUX. His research is focused on the design of RFICs. Dr. Rivet has publications in top ranked journals (JSSC, TCAS-II), international conferences (RFIC, RWS), national conferences (JNM) and holds 9 patents. He received the Best Paper Award at Software Defined Radio Forum in 2008 at Washington DC, USA. Yoan VEYRAC received the Master degree in 2012 from the Electrical Engineering School of Bordeaux, France (ENSEIRB-MATMECA). He is currently pursuing the PhD degree at the IMS laboratory (Bordeaux), in the circuits and systems team. He is specialized in RF architectures and circuit design, especially in the field of software radio transmitters. Nassim BOUASSIDA received the Master degree in 2012 from the University of BORDEAUX, France. He is with STMicroelectronics as a hardware engineer and PhD student at the IMS laboratory (Bordeaux), in the Circuits and Systems team. He is currently working on software radio transmitters. References [1] F. Rivet, Y. Deval, J--‐B. Begueret, D. Dallet, P. Cathelin, D. Belot, “The experimental demonstration of a SASP--‐based full Software Radio Receiver”, IEEE Journal of Solid State Circuits (JSSC), vol 45, pp 979 – 988, May 2010. [2] Y. Veyrac, F. Rivet, Y. Deval, D. Dallet, P. Garrec, R. Montigny, “The Riemann Pump: a Concurrent Transmitter in GaN Technology “, IEEE International Conference on Electronics, Circuits, and Systems, Marseille, France, December 2014. [3] N. Bouassida, F. Rivet, Y. Deval, D. Dallet, D. Belot, “Un émetteur radio logicielle intégrale à base de recombinaison d’harmoniques”, Journées Nationales du Réseau des Doctorants en Microélectronique (JNRDM’14), Lille, France, May 26--‐28, 2014.
4. Substrate integrated waveguides: from PCB to microelectronics technologies Sunday 7 June 2015, afternoon Speaker: Ke WU (Poly-Grames Research Center, Department of Electrical Engineering Center for Radiofrequency Electronics Research of Quebec (CREER), Polytechnique Montréal, Québec, Canada). Abstract Recent research effort in exploring and exploiting substrate integrated circuits (SICs) has fundamentally changed the landscape of high-frequency circuit and system integration and development. In particular, substrate integrated waveguide (SIW) technology, which is part of the SICs family, has created a great enthusiasm in the applied electromagnetic and integrated circuit community worldwide for a wide range of low cost-enabled commercial and high-performance-oriented defense applications from MHz to THz. The critical enablers in this disruptive technology lie in the successful hybrid and monolithic planarization and integration of non-planar metallo-dielectric waveguides through the structure synthesis made of various processing techniques. The early SIW technology development has been pushed forward and has become matured thanks to the development of a series of single layered and multi-layered printed circuit board (PCB) processing techniques and hybrid multilayered micro-fabrication processing techniques such as LTCC and photo-imageable processing techniques. Those fabrication techniques have contributed to the fast-paced progress of passive integrated components, circuits and antennas. This paper reviews the recent developments and accomplishments of various SIW antenna and circuit techniques with emphasis on PCB-based design platforms. Practical examples are shown for their applications in the design and development of innovative integrated passive circuits and antenna arrays for applications ranging from MHz to THz. Emerging and future development trends of SIW techniques are discussed with special interest in the use and integration of smart and active materials as well as semiconductor-based microelectronic processing techniques such as CMOS schemes over millimeter-wave and terahertz frequency ranges. It is anticipated that emerging CMOS-based “SIW and SICs” will prevail in the decades to come. This presentation will also deal with a number of grand challenging issues and the arising of unprecedented problems in passive-active circuits integrations. Biography Ke Wu received B.Sc. degree (with distinction) in radio engineering from Nanjing Institute of Technology (now Southeast University), China, in 1982 and D.E.A. and Ph.D. degrees in optics, optoelectronics, and microwave engineering (with distinction) from Institut National Polytechnique de Grenoble (INPG) and University of Grenoble, France, in 1984 and 1987, respectively. He is professor of electrical engineering and Tier-I Canada Research Chair in RF and millimeter-wave engineering at the Ecole Polytechnique (University of Montreal). He holds an honorary professorship at the Nanjing University of Science and Technology, the Nanjing University of Post Telecommunication, and the City University of Hong Kong, China. He has been the Director of the Poly-Grames Research Center. He was the founding Director of the Center for Radiofrequency Electronics Research of Quebec (FRQNT Regroupement stratégique) for 2008-2014. He has also held guest and visiting professorship at many universities around the world. He has authored or co-authored over 995 referred papers, and a number of books/book chapters and filed more than 30 patents. He has already graduated 48 Ph.D and 83 M. Sc. A students. His current research interests involve substrate integrated circuits (SICs), antenna arrays, advanced CAD and modeling techniques, wireless power transmission and harvesting, and development of low-cost RF and millimeter-wave transceivers and sensors for wireless systems, security techniques and biomedical applications. He is also interested in the modeling and design of millimeter-wave photonic circuits and systems. Dr. Wu is a member of Electromagnetics Academy, the Sigma Xi Honorary Society, and the URSI. He has held key positions in and has served on various panels and international committees including the chair of technical program committees, international steering committees and international conferences/symposia. In particular, he was the general chair of the 2012 IEEE MTT-S (Microwave Theory and Techniques Society) International Microwave Symposium. He has served on the editorial/review boards of many technical journals, transactions, proceedings and letters as well as scientific encyclopedia including editors and guest editors. He is currently the chair of the joint IEEE chapters of MTTS/APS/LEOS in Montreal. Dr. Wu is an elected IEEE MTT-S AdCom member for 2006-2015 and served as Chair of the IEEE MTT-S Transnational Committee, Member and Geographic Activities (MGA) Committee and Technical Coordinating Committee (TCC) among many other AdCom functions. He is the 2015 IEEE MTT-S President-Elect and will become the 2016 IEEE MTT-S President. Dr. Wu is the inaugural three-year representative of North America as Member of the European Microwave Association (EuMA) General Assembly. He was the recipient of many awards and prizes including the inaugural IEEE MTT-S Outstanding Young Engineer Award, the 2004 Fessenden Medal of the IEEE Canada and the 2009 Thomas W. Eadie Medal of the Royal Society of Canada, the Queen Elizabeth II Diamond Jubilee Medal, the 2013 FCCP Education Foundation Award of Merit, the 2014 IEEE MTT-S Microwave Application Award, the 2014 IEEE MTT-S Microwave Application Award, and the 2014 Marie-Victorin Prize (Prix du Quebec - the highest distinction of Québec in the natural sciences and engineering). He is a Fellow of the IEEE, a Fellow of the Canadian Academy of Engineering (CAE) and a Fellow of the Royal Society of Canada (The Canadian Academy of the Sciences and Humanities). He was an IEEE MTT-S Distinguished Microwave Lecturer from Jan. 2009 to Dec. 2011. |
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